1. Field of the Invention
The present invention relates to a row decoder and in particular to a row decoder for a flash EEPROM.
2. Description of the Related Art
Flash EEPROMs are characterized by electrical erasability and reprogrammability. Since flash EEPROMs (hereafter referred to as flash memories) fit any application that requires high density arrangement and reprogrammability, many investigations have been undertaken recently. Seki et al. presented a paper on an internal erase and erase-verify control system for a flash memory in the IEEE Journal of Solid-State Circuits, Vol. 25, No. 5, pp. 1147-1151, 1990. The flash memory used by the authors is of the one-transistor type with a stacked gate structure. FIG. 1 is a schematic cross-sectional view of the memory cell. N-type drain 202 and source 203 are formed in P-type substrate 201, and control gate 205 and floating gate 204 insulated by insulating layer 206 are provided above the channel region of substrate 201. An oxide layer approximately 10 nm thick, commonly called a tunnel oxide layer, is formed between floating gate 204 and the channel region.
Writing to the memory cell is effected both by applying a high potential (typically 12 V) to control gate 205 and drain 202, and by applying the ground potential to source 203, whereby an avalanche breakdown is caused, allowing hot electrons created by the breakdown to inject into floating gate 204. Erasure of written data is effected by applying the ground potential to control gate 205 and the high potential to source 203 with drain 202 floated, allowing electrons to discharge from floating gate 204 through the Flower-Nordheim tunneling.
In the method of erasing a flash memory described above, however, desired erase characteristics cannot always be obtained, because an erasure voltage is not applicable to source 203 beyond a junction breakdown voltage for the N-type diffusion region which forms source 203. In order to solve this problem, Miyawaki et al. proposed an erasing and row decoding scheme for a low supply-voltage operation of 16 Mb/64 Mb flash EEPROMs, published in the Digest of Technical Papers presented in the 1991 Symposium on VLSI Circuits held in Oiso, Japan (IEEE CAT. No. 91 CH 3018.9).
FIG. 2 shows the circuit diagram of the row decoding circuit devised by Miyawaki et al. The circuit is composed of an RX generator (a booster voltage generator), a row decoder, P-channel transfer gate T1 and P-channel transfer gate T2. Boosted voltage RX generated by the RX generator is applied to the upper-side drain of serially connected N-channel MOSFETs T3, T4 of the row decoder and is delivered to word line WL through P-channel transfer gate T1.
TABLE 1 ______________________________________ WL RX PG1 PW PG2 NVPP ______________________________________ Read V.sub.BST V.sub.BST V.sub.NEG V.sub.BST V.sub.BST GND Program V.sub.PP V.sub.PPB V.sub.NEG V.sub.PPB V.sub.PPB GND Erase V.sub.ERS GND GND GND V.sub.ERS V.sub.ERS ______________________________________ V.sub.BST : boosted voltage V.sub.PPB : boosted V.sub.PP V.sub.ERS : -12 V V.sub.NEG : negative voltage
As is known from the operating conditions shown in Table 1, transfer gate T1 is turned on during the read and write time in order to transfer read voltage V.sub.BST and write voltage V.sub.PPB respectively, to word line WL, and is turned off during the erase time in order to shut off negative erasure voltage V.sub.ERS from transmitting to the row decoder. Conversely, transfer gate T2 is turned off during read and write times and is turned on during the erase time in order to transfer negative erasure voltage V.sub.ERS to word line WL.
It is to be noted that P-channel MOSFETs are used for transfer gates T1, T2 in order to prevent a junction leakage current which may be caused between the drain.source diffusion region and the substrate when a negative erasure voltage is applied to word line WL during erase operation. Since gate voltage PG2 of transfer gate T2 is equal to source voltage N.sub.VPP (=V.sub.ERS), the erasure voltage applied to word line WL during the erase operation is V.sub.ERS -(-V.sub.th)=V.sub.ERS +V.sub.th, where -V.sub.th denotes the threshold voltage of P-type transfer gate T2 for grounded back gate bias PW. For example, if V.sub.ERS =-12 V and -V.sub.th =-2 V, the actual voltage applied to word line is -10 V which is V.sub.th (=2 V) higher than V.sub.ERS.
FIG. 3 shows a diagrammatic representation of the operating condition of the memory cell according to the conventional row decoding scheme and to that proposed by Miyawaki et al. By virtue of this scheme Miyawaki et al. were able to attain low power and high speed erase operation by making use of a source voltage of only 5 V.
A level shift circuit for a CMOS EPROM is presented in the paper of W. Ip et al. (Digest of Technical Papers, 1984 IEEE International Solid-State Circuit Conference, pp. 138 and 139). FIG. 4 shows a row decoding circuit including level shift circuit 2 and transfer gates P1, P2, wherein level shift circuit 2 is an application of the level shift circuit above and transfer gates P1, P2 correspond to transfer gates T1, T2 shown in FIG. 2. Level shift circuit 2 is intended to establish in level-shift line X.sub.SFT, dc voltage V.sub.SFT predetermined so as to act as read voltage V.sub.R and write voltage V.sub.W during read operation and write operation, respectively. Transfer gates P1 and P2 act identically with transfer gates T1 and T2, respectively, described above. Level shift circuit 2 is provided with transfer gate N21 of an N-channel depletion MOSFET, which is directed both to transferring the output of row decoder 1 to level-shift line X.sub.SFT and to shutting off write voltage from being transmitted to row decoder 1, as will be described below. CMOS inverter 23 is made up of P-channel MOSFET P21 and N-channel MOSFET N22, having a gate input connected to level-shift line X.sub.SFT, upper- and lower-side sources supplied with dc supply voltages VD and VSS, respectively. The transition threshold voltage of inverter 23 is set at a voltage below V.sub.th, where - V.sub.th denotes the gate.source threshold voltage of transfer gate N21. D.sub.C supply voltage VD is set at read voltage V.sub.R of high level H (preferably 5 V) during read operation and at write voltage V.sub.W (preferably 12 V) during write operation. Level-shifter transistor P22 is a P-channel MOSFET with the source connected to dc supply voltage VD, the gate supplied with output g of inverter 23 and the drain connected to level-shift line X.sub.SFT.
Transfer gate P1 is a P-channel MOSFET, which transfers dc voltage V.sub.SFT to word line X11 during read operation and write operation and shuts off level-shift line X.sub.SFT from word line X11 during erase operation. Transfer gate P2 is a P-channel MOSFET which transfers negative erasure voltage VS=V.sub.ERS to word line X11 during erase operation and shuts off word line X11 from the erasure voltage supply during read operation and write operation.
TABLE 2 ______________________________________ VG1 VG2 VG21 VD VS VB1 VB2 ______________________________________ Read V.sub.NEG H H V.sub.R H H H Write V.sub.NEG V.sub.W L V.sub.W V.sub.W V.sub.W V.sub.W Erase L V.sub.ERS H H V.sub.ERS L L ______________________________________
In read operation, gate voltage VG1 of transfer gate P1 is set at negative voltage V.sub.NEG (preferably -5 V), and gate voltages VG21, VG2 of transfer gates N21, P2, respectively, back gate biases VB1, VB2 of transfer gates P1, P2, respectively, and dc supply voltages VD, VS are set at high level H (normally 5 V.) This voltage setting turns transfer gate P1 on and transfer gate P2 off. Applying high level H to the gate of N-channel depletion transfer gate N21 causes the transfer gate to turn on regardless of the logic level of the row decoder output. Further, applying high-level back gate voltages VB1, VB2 to N-type wells of transfer gates P1, P2 prevents junction leakage currents between the N-type wells and P-type drain.source diffusion regions from flowing. When word line X11 is selected for read operation, row decoder 1 provides a decode signal of high level H which is applied to the input of CMOS inverter 23 through transfer gate N21. Since the transition threshold voltage of CMOS inverter 23 is below H, CMOS inverter 23 delivers low level output g, which causes P-channel level-shifter transistor P22 turn on, causing dc supply voltage VD, i.e., read voltage V.sub.R, to be established in level-shift line X.sub.SFT. Read voltage V.sub.R, is then transmitted to row line X11 through transfer gate P1.
When word line X11 is not selected, row decoder 1 delivers a decode signal of low level L which is applied to the input of CMOS inverter 23 through transfer gate N21, causing output g of CMOS inverter 23 to be at dc supply voltage VD (=H), with the result that level shifter transistor P22 is cut off. Thus, low level L delivered from row decoder 1 is transmitted to word line X11 through transfer gates N21 and P1.
Accordingly, CMOS inverter 23 acts as a detector for detecting the logic level of the decode signal, and level-shifter transistor acts as a switching transistor to connect dc supply voltage VD to transfer gate P1.
In write operation, gate voltage VG1 of transfer gate P1 is set at negative voltage V.sub.NEG (preferably -5 V), gate voltage VG21 of transfer gate N21 is set at low level L (the ground potential), and each of back gate biases VB1 and VB2 of transfer gates P1 and P2, respectively, gate voltage VG2 of transfer gate P2 and dc supply voltages VD and VS are set at write voltage V.sub.W (preferably 10 V). This voltage setting turns transfer gate P1 on and transfer gate P2 off. Further, N-channel depletion transfer gate N21 is initially (it is assumed that the output of row decoder 1 is initially at a low level) caused to be on. Again, applying write voltage V.sub.W to N-type wells of transfer gates P1, P2 as back gate biases VB1, VB2 prevents creation of junction leakage currents. As in read operation, when word line X11 is selected for write operation, row decoder 1 delivers high level H, which causes level shift circuit to deliver write voltage V.sub.W to level shift line X.sub.SFT. When dc voltage V.sub.SFT rises above threshold voltage V.sub.th, transfer gate N21 is cut off, preventing write voltage V.sub.W from being applied to row decoder 1. Write voltage V.sub.W is transmitted to word line X11 through transfer gate P1.
In erase operation, each of gate voltage VG21 of transfer gate N21 and dc supply voltage VD is set at high level H, gate voltage VG1 of transfer gate P1, and back gate biases VB1, VB2 of transfer gates P1, P2, respectively, are set at low level L, and each of dc supply voltage VS and control gate voltage VG2 of transfer gate P2 is set at erasure voltage V.sub.ERS (preferably -10 V). This voltage setting causes transfer gates N21 and P2 to turn on and causes transfer gate P1 to turn off, if dc voltage V.sub.SFT is at low level L. In order to have dc voltage V.sub.SFT of low level L, means for causing the output of row decoder 1 to be at low level L during erase operation (not shown in FIG. 4) is provided in row decoder 1. In this way, dc supply voltage VS (=erasure voltage V.sub.ERS) is applied to row line X11 through transfer gate P2 without any transfer of erasure voltage V.sub.ERS to level-shift line X.sub.SFT.
A problem encounted in the row decoding circuits of prior art shown in FIG. 4 is that, since the gate of transfer gate P2 is not coupled with row decoder 1, the action of transfer gate P2 for erase operation does not respond to the decoding action of row decoder 1.
Another problem is that the negative erasure voltage actually applied to the word line is lower in absolute value than the negative voltage VS supplied to P-channel transfer gate P2 by at least V.sub.TH, as described above. This voltage loss takes place inherently in using a P-channel MOSFET, because the gate potential has to be lower than the source potential by at least V.sub.TH in order for the P-channel MOSFET to be conductive. However, it is quite common to use a P-channel MOSFET for a negative-voltage transmission rather than an N-channel MOSFET to avoid creating a junction leakage current between the source.drain diffusion region and the substrate. Nevertheless, the voltage loss is an important problem to be solved in order to use the internal negative voltage source of an EEPROM device efficiently.
A further problem encountered in the prior art is that none of the prior art row decoding circuits is capable of selecting one or more word lines from a group of word lines for erase operation.